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cloud.google.com·7h ago
AI Research
arXiv CS.AI·Aug 17·5 min read
PPAPlace: Differentiable Cross-Stage Objectives for Chip Placement Optimization
TL;DR
PPAPlace introduces a novel approach to chip placement optimization by using a differentiable surrogate model that predicts post-route performance metrics. It significantly improves timing metrics by 22% and 51% over traditional methods while maintaining power and routability.
✦ Why It Matters
Implement PPAPlace in your chip design workflow to enhance timing performance without sacrificing power or routability.
Key Takeaways
- Adopt PPAPlace for improved chip placement outcomes.
- Utilize dual-stream predictors for better timing predictions.
- Focus on post-global-routing metrics for training models.
- Preserve power and routability while optimizing performance.
How It Works
PPAPlace uses a dual-stream architecture that integrates graph attention over the chip netlist with spatial convolution on the placement grid. This allows the model to effectively predict post-route performance metrics by leveraging gradients that flow back to the cell coordinates, enabling precise adjustments during optimization.