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cloud.google.com·8h ago
AI Research
arXiv CS.AI·Sep 4·5 min read
LevelSyn: Physical-Aware Logic Synthesis via Level-Asynchronous Graph Neural Networks
TL;DR
LevelSyn is a new framework for logic synthesis that integrates physical design considerations using a level-asynchronous Graph Neural Network. It achieves significant improvements in power reduction and timing delay, enhancing design efficiency in integrated circuits.
✦ Why It Matters
Consider adopting LevelSyn for your next integrated circuit design project to enhance efficiency and reduce errors.
Key Takeaways
- Implement LevelSyn for improved logic synthesis in integrated circuits.
- Utilize level-aligned subgraph partitioning to manage large designs.
- Leverage the power reduction and timing improvements in your projects.
- Reduce design rule check violations to accelerate design closure.
How It Works
LevelSyn employs a level-asynchronous Graph Neural Network (GNN) to analyze the structural and directional semantics of And-Inverter Graphs (AIGs). This allows it to predict high-fidelity gate coordinates, which are crucial for optimizing physical design.
The framework also incorporates a wirelength-driven optimization engine that enhances the synthesis process by focusing on minimizing wire lengths, thereby improving overall circuit performance.